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february 2009 rev 9 1/31 1 m48t08 m48t08y, m48t18 5 v, 64 kbit (8 kb x 8) timekeeper ? sram features integrated ultra low power sram, real-time clock, power-fail control circuit, and battery bytewide? ram-like clock access bcd coded year, month, day, date, hours, minutes, and seconds typical clock accuracy of 1 minute a month, at 25c automatic power-fail chip deselect and write protection write protect v pfd = power-fail deselect voltage): ?m48t08: v cc = 4.75 to 5.5 v 4.5 v v pfd 4.75 v ? m48t18/t08y: v cc = 4.5 to 5.5 v 4.2 v v pfd 4.5 v software controlled clock calibration for high accuracy applications self-contained battery and crystal in the caphat? dip package packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery and crystal pin and function compatible with ds1643 and jedec standard 8 k x 8 srams rohs compliant ? lead-free second level interconnect 28 1 pcdip28 (pc) battery/crystal caphat? 28 1 snaphat ? (sh) battery/crystal soh28 (mh) www.st.com
contents m48t08, m48t08y, m48t18 2/31 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 power-fail interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m48t08, m48t08y, m48t18 list of tables 3/31 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. read mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. pcdip28 ? 28-pin plastic dip, battery caphat?, package mech. data . . . . . . . . . . . . . 23 table 13. soh28 ? 28-lead plastic so, 4-socket battery snaphat ? , package mech. data. . . . . . . 24 table 14. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package mech. data . . . . . 25 table 15. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package mech. data . . . . 26 table 16. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. snaphat ? battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of figures m48t08, m48t08y, m48t18 4/31 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. write enable controlled, write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 9. clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. power down/up mode ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. pcdip28 ? 28-pin plastic dip, battery caphat?, package outline . . . . . . . . . . . . . . . . . 23 figure 14. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package outline . . . 24 figure 15. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package outline. . . . . . . . . 25 figure 16. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package outline. . . . . . . . 26 figure 17. recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m48t08, m48t08y, m48t18 description 5/31 1 description the m48t08/18/08y timekeeper ? ram is an 8 k x 8 non-volatile static ram and real time clock which is pin and functional compatible with the ds1643. the monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. the m48t08/18/08y is a non-volatile pin and function equivalent to any jedec standard 8 k x 8 sram. it also easily fits into many rom, eprom , and eeprom sockets, providing the non-volatility of proms without any requirement for special write timing or limitations on the number of writes that can be performed. the 28-pin, 600 mil dip caphat? houses the m48t08/18/08y silicon with a quartz crystal and a long-life lithium button cell in a single package. the 28-pin, 330 mil soic provides sockets with gold plated contacts at both ends for direct connection to a separate snaphat ? housing containing the battery and crystal. the unique design allows the snaphat battery package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. the snaphat housing is keyed to prevent reverse insertion. the soic and battery/crystal packages are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead soic, the battery/crystal package (e.g., snaphat) part number is ?m4t28-br12sh? or ?m4t32-br12sh? (see table 17 on page 28 ). figure 1. logic diagram ai01020 13 a0-a12 w dq0-dq7 v cc m48t08 m48t08y m48t18 g e2 v ss 8 e1 int
description m48t08, m48t08y, m48t18 6/31 table 1. signal names figure 2. dip connections a0-a12 address inputs dq0-dq7 data inputs / outputs int power fail interrupt (open drain) e1 chip enable 1 e2 chip enable 2 g output enable w write enable v cc supply voltage v ss ground a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc ai01182 m48t08 m48t18 8 1 2 3 4 5 6 7 9 10 11 12 13 14 16 15 28 27 26 25 24 23 22 21 20 19 18 17
m48t08, m48t08y, m48t18 description 7/31 figure 3. soic connections figure 4. block diagram ai01021b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 a1 a0 dq0 a7 a4 a3 a2 a6 a5 e2 a10 a8 a9 dq7 w a11 g e1 dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 int v cc m48t08y ai01333 lithium cell oscillator and clock chain v pfd int v cc v ss 32,768 hz crystal voltage sense and switching circuitry 8 x 8 biport sram array 8184 x 8 sram array a0-a12 dq0-dq7 e1 e2 w g power
operation modes m48t08, m48t08y, m48t18 8/31 2 operation modes as figure 4 on page 7 shows, the static memory array and the quartz-controlled clock oscillator of the m48t08 /18/08y are integr ated on one silicon chip. the two circuits are interconnected at the upper eight memory locations to provide user accessible bytewide? clock information in the bytes with addresses 1ff8h-1fffh. the clock locations contain the year, month, date, day, hour, minute, and second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. byte 1ff8h is the clock control register. this byte controls user access to the clock information and also stores the clock calibration setting. the eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of biport? read/write memory cells. the m48t08/18/08y includes a clock control circuit which updates the clock bytes with current information once per second. the information can be accessed by the user in the same manner as any other location in the static memory array. the m48t08/18/08y also has its own power-fail detect circuit. the control circuitry constantly monitors the single 5 v supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram , providing a high degree of data security in the midst of unpredictable system operation brought on by low v cc . as v cc falls below the battery backup switchover voltage (v so ), the control circuitry connects the battery which maintains data and clock operat ion until valid power returns. table 2. operating modes note: x = v ih or v il ; v so = battery backup switchover voltage. 2.1 read mode the m48t08/18/08y is in the read mode whenever w (write enable) is high, e1 (chip enable 1) is low, and e2 (chip enable 2) is high. the device architecture allows ripple- through access of data from eight of 65,536 locations in the static storage array. thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. valid data will be availabl e at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e1 , e2, and g access times are also satisfied. if the e1 , e2 and g access times are not met, valid data will mode v cc e1 e2 g w dq0-dq7 power deselect 4.75 to 5.5 v or 4.5 to 5.5 v v ih x x x high z standby deselect x v il x x high z standby write v il v ih xv il d in active read v il v ih v il v ih d out active read v il v ih v ih v ih high z active deselect v so to v pfd (min) (1) 1. see table 11 on page 22 for details. xxxxhigh zcmos standby deselect v so (1) x x x x high z battery backup mode
m48t08, m48t08y, m48t18 operation modes 9/31 be available after the latter of the chip enable access times (t e1lqv or t e2hqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e1 , e2 and g . if the outputs are activated before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address inputs are changed while e1 , e2 and g remain active, output data will remain valid for outp ut data hold time (t axqx ) but will go indeterm inate until the next address access. figure 5. read mode ac waveforms note: write enable (w ) = high. ai00962 tavav tavqv taxqx te1lqv te1lqx te1hqz tglqv tglqx tghqz valid a0-a12 e1 g dq0-dq7 te2hqv te2hqx valid te2lqz e2
operation modes m48t08, m48t08y, m48t18 10/31 table 3. read mode ac characteristics note: valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). 2.2 write mode the m48t08/18/08y is in the write mode whenever w , e1 , and e2 are active. the start of a write is referenced from the latter occurring falling edge of w or e1 , or the rising edge of e2. a write is terminated by the earlier rising edge of w or e1 , or the falling edge of e2. the addresses must be held valid throughout the cycle. e1 or w must return high or e2 low for a minimum of t e1hax or t e2lax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t dvwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; however, if the output bus has been activated by a low on e1 and g and a high on e2, a low on w will disable the outputs t wlqz after w falls. symbol parameter (1) m48t08/m48t18/t08y unit ?100/?10 (t08y) ?150/?15 (t08y) min max min max t avav read cycle time 100 150 ns t avqv address valid to output valid 100 150 ns t e1lqv chip enable 1 low to output valid 100 150 ns t e2hqv chip enable 2 high to output valid 100 150 ns t glqv output enable low to output valid 50 75 ns t e1lqx chip enable 1 low to output transition 10 10 ns t e2hqx chip enable 2 high to output transition 10 10 ns t glqx output enable low to output transition 5 5 ns t e1hqz chip enable 1 high to output hi-z 50 75 ns t e2lqz chip enable 2 low to output hi-z 50 75 ns t ghqz output enable high to output hi-z 40 60 ns t axqx address transition to output transition 5 5 ns
m48t08, m48t08y, m48t18 operation modes 11/31 figure 6. write enable controlled, write ac waveform figure 7. chip enable controlled, write ac waveforms ai00963 tavav twhax tdvwh data input a0-a12 e1 w dq0-dq7 valid e2 tavwh tave1l tave2h twlwh tavwl twlqz twhdx twhqx ai00964b tavav te1hax tdve1h tdve2l a0-a12 e1 w dq0-dq7 valid e2 tave1h tave1l tavwl tave2l te1le1h te2lax tave2h te2he2l te1hdx te2ldx data input
operation modes m48t08, m48t08y, m48t18 12/31 table 4. write mode ac characteristics 2.3 data retention mode with valid v cc applied, the m48t08/18/08y operates as a conventional bytewide? static ram. should the supply voltage decay, the ra m will automatically power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as ?don't care.? note: a power failure during a write cycle may corr upt data at the curren tly addressed location, but does not jeopardize the rest of the ram's content. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48t08/18/08y may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . therefore, decoupling of the power supply lines is recommended. symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48t08/m48t18/t08y unit ?100/?10 (t08y) ?150/?15 (t08y) minmaxminmax t avav write cycle time 100 150 ns t avwl address valid to write enable low 0 0 ns t ave1l address valid to chip enable 1 low 0 0 ns t ave2h address valid to chip enable 2 high 0 0 ns t wlwh write enable pulse width 80 100 ns t e1le1h chip enable 1 low to chip enable 1 high 80 130 ns t e2he2l chip enable 2 high to chip enable 2 low 80 130 ns t whax write enable high to address transition 10 10 ns t e1hax chip enable 1 high to address transition 10 10 ns t e2lax chip enable 2 low to address transition 10 10 ns t dvwh input valid to write enable high 50 70 ns t dve1h input valid to chip enable 1 high 50 70 ns t dve2l input valid to chip enable 2 low 50 70 ns t whdx write enable high to input transition 5 5 ns t e1hdx chip enable 1 high to input transition 5 5 ns t e2ldx chip enable 2 low to input transition 5 5 ns t wlqz write enable low to output hi-z 50 70 ns t avwh address valid to write enable high 80 130 ns t ave1h address valid to chip enable 1 high 80 130 ns t ave2l address valid to chip enable 2 low 80 130 ns t whqx write enable high to output transition 10 10 ns
m48t08, m48t08y, m48t18 operation modes 13/31 when v cc drops below v so , the control circuit switches power to the internal battery which preserves data and powers the clock. the inte rnal button cell will ma intain data in the m48t08/18/08y for an accumulated period of at least 10 years when v cc is less than v so . note: requires use of m4t32-br12sh snaphat ? top when using the soh28 package. as system power returns and v cc rises above v so , the battery is disconnected and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). e1 should be kept high or e2 low as v cc rises past v pfd (min) to prevent inadvertent write cycles prior to system stabilization. normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. 2.4 power-fail interrupt pin the m48t08/18/08y continuously monitors v cc . when v cc falls to the power-fail detect trip point, an interrupt is immediately generated. an internal clock provides a delay of between 10 s and 40 s before automatically deselecting the m48t08/18/08y. the int pin is an open drain output and requires an external pull-up resistor, even if the interrupt output function is not being used.
clock operations m48t08, m48t08y, m48t18 14/31 3 clock operations 3.1 reading the clock updates to the timekeeper ? registers should be halted before clock data is read to prevent reading data in tran sition. the biport? timekeeper cells in the ram array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. updating is halted when a '1' is written to the read bit, the seventh bit in the control register. as long as a '1' remains in that position, updating is halted. after a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. all of the timekeeper register s are updated simult aneously. a halt will not interrupt an update in progress. updating is within a second after the bit is reset to a '0.' 3.2 setting the clock the eighth bit of the control register is the wr ite bit. setting the write bit to a '1,' like the read bit, halts updates to the timekeeper regi sters. the user can then load them with the correct day, date, and time data in 24-hour bcd format (on ta bl e 5 ). resetting the write bit to a '0' then transfers the values of all time registers (1ff9h-1fffh) to the actual timekeeper counters and allows normal operation to resume . the ft bit and the bits marked as '0' in ta bl e 5 must be written to '0' to allow for normal timekeeper and ram operation. see the application no te an923, ?timekeeper ? rolling into the 21 st century? for information on century rollover.
m48t08, m48t08y, m48t18 clock operations 15/31 table 5. register map note: s = sign bit ft = frequency test bit (set to '0' for normal clock operation) r = read bit w = write bit st = stop bit 0 = must be set to '0' 3.3 stopping and starting the oscillator the oscillator may be stopped at any time. if the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. the stop bit (st) is the msb of the seconds register. setting it to a '1' stops the oscillator. the m48t08/18/08y (in th e pcdip28 package) is shipped from stmicroelectronics with the stop bit set to a '1.' when reset to a '0,' the m48t08/18/08y oscillator starts within one second. note: to guarantee oscillator startup after initial power-up, first write the stop bit (st) to '1,' then reset to '0.' 3.4 calibrating the clock the m48t08/18/08y is dr iven by a quartz-controlled oscilla tor with a nominal frequency of 32,768 hz. a typical m48t08/18/08y is accurate within 1 minute per month at 25c without calibration. the devices are te sted not to exceed 35 ppm (parts per millio n) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. with the calibration bits properly set, the accuracy of each m48t08/18/08y improves to better than +1/?2 ppm at 25c. the oscillation rate of any cryst al changes with temperature. figure 8 on page 17 shows the frequency error that can be expected at vari ous temperatures. most clock chips compensate for crystal frequency and temperature shift error with cumbersome ?trim? capacitors. the m48t08/18/08y design, however, employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscilla tor divider circuit at th e divide by 256 stage, as shown in figure 9 on page 17 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into address data function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 1fffh 10 years year year 00-99 1ffeh 0 0 0 10 m month month 01-12 1ffdh 0 0 10 date date date 01-31 1ffch 0 ft 0 0 0 day day 01-07 1ffbh 0 0 10 hours hours hours 00-23 1ffah 0 10 minutes minutes minutes 00-59 1ff9h st 10 seconds seconds seconds 00-59 1ff8h w r s calibration control
clock operations m48t08, m48t08y, m48t18 16/31 the five-bit calibration byte found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration byte occupies the five lower order bits in the control register. this byte can be set to represent any value between 0 and 31 in binary form. the sixth bit is the sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or leng thened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actu al oscillator cycles; that is +4.068 or ?2.034 ppm of adjustment per calibration step in the calibration register. assu ming that the oscillator is in fact running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m48t08/18/08y may require. the first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like wwv broadcasts). while that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. all the designer has to do is provide a simple utilit y that accesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. when the frequency test (ft) bit, the seventh-most significant bit in the day register, is set to a '1,' and the oscillator is runni ng at 32,768 hz, the lsb (dq0) of the seconds register will toggle at 512 hz. any deviat ion from 512 hz indicates the degree and direction of oscillator frequency shif t at the test temperature. for example, a reading of 512.01024 hz would indicate a +2 0 ppm oscillator frequency error, requiring a ?10 (wr001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output frequency. the device must be selected and addresses must be stable at address 1ff9h when reading the 512 hz on dq0. the lsb of the seconds register is monitored by holding the m48t08/18/08y in an extended read of the seconds register, but without having the read bit set. the ft bit must be reset to '0' for normal clock operations to resume. for more information on calibration, see the application note an934, ?timekeeper ? calibration.?
m48t08, m48t08y, m48t18 clock operations 17/31 figure 8. crystal accuracy across temperature figure 9. clock calibration 3.5 v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store energy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low goin g spikes are generated or energy will be absorbed when overshoots occur. a ceramic bypass capacitor value of 0.1 f (as shown in figure 10 ) is recommended in order to provide the needed filtering. in addition to transients that are caused by normal sram operation, power cycling can generate negative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, it is recommended to connect a schottky diode from v cc to v ss (cathode connected to v cc , anode to v ss ). schottky diode ai02124 -80 -60 -100 -40 -20 0 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 f = -0.038 (t - t 0 ) 2 10% f ppm c 2 t 0 = 25 c ppm c ai00594b normal positive calibration negative calibration
clock operations m48t08, m48t08y, m48t18 18/31 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount. figure 10. supply voltage protection ai02169 v cc 0.1 f device v cc v ss
m48t08, m48t08y, m48t18 maximum ratings 19/31 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings caution: negative undershoots below ?0.3 v are not allowed on any pin while in the battery backup mode. caution: do not wave solder soic to avoid damaging snaphat ? sockets. symbol parameter value unit t a ambient operating temperature 0 to 70 c t stg storage temperature (v cc off, oscillator off) ?40 to 85 c t sld (1)(2)(3) 1. for dip package: soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 seconds). 2. for so package, standard (snpb) lead finish: reflow at peak temper ature of 225c (the time above 220c must not exceed 20 seconds). 3. for so package, lead-free (pb-free ) lead finish: reflow at peak temperature of 260c (the time above 255c must not exceed 30 seconds). lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.3 to 7 v v cc supply voltage ?0.3 to 7 v i o output current 20 ma p d power dissipation 1 w
dc and ac parameters m48t08, m48t08y, m48t18 20/31 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. table 7. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 11. ac testing load circuit table 8. capacitance parameter m48t08 m48t18/t08y unit supply voltage (v cc ) 4.75 to 5.5 4.5 to 5.5 v ambient operating temperature (t a ) 0 to 70 0 to 70 c load capacitance (c l ) 100 100 pf input rise and fall times 5 5ns input pulse voltages 0 to 3 0 to 3 v input and output timing ref. voltages 1.5 1.5 v symbol parameter (1)(2) 1. effective capacitance m easured with power supply at 5 v; sampled only, not 100% tested. 2. at 25c, f = 1 mhz. min max unit c in input capacitance 10 pf c io (3) 3. outputs deselected. input / output capacitance 10 pf ai01019 5v out c l = 100pf c l includes jig capacitance 1.8k device under test 1k
m48t08, m48t08y, m48t18 dc and ac parameters 21/31 table 9. dc characteristics figure 12. power down/up mode ac waveforms note: inputs may or may not be recognized at this time. caution should be taken to keep e1 high or e2 low as v cc rises past v pfd (min). some systems may pe rform inadvertent write cycles after v cc rises above v pfd (min) but before normal system operations begin. even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. symbol parameter test condition (1) 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). m48t08/m48t18/t08y unit min max i li input leakage current 0v v in v cc 1 a i lo (2) 2. outputs deselected. output leakage current 0v v out v cc 1 a i cc supply current outputs open 80 ma i cc1 (3) 3. measured with control bits set as follows: r = '1'; w, st, ft = '0.' supply current (standby) ttl e1 = v ih, e2 = v il 3ma i cc2 (3) supply current (standby) cmos e1 = v cc ? 0.2v, e2 = v ss + 0.2v 3ma v il input low voltage ?0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1 ma 0.4 v output low voltage (int ) (4) 4. the int pin is open drain. i ol = 0.5 ma 0.4 v v oh output high voltage i oh = ?1 ma 2.4 v ai00566 v cc inputs int (per control input) outputs don't care high-z tf tfb tpfx tr tpfh trec tpd trb tdr valid valid note (per control input) recognized recognized v pfd (max) v pfd (min) v so
dc and ac parameters m48t08, m48t08y, m48t18 22/31 table 10. power down/up ac characteristics table 11. power down/up trip points dc characteristics symbol parameter (1) 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). min max unit t pd e1 or w at v ih or e2 at v il before power-down 0 s t f (2) 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200 s after v cc passes v pfd (min). v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0 s t rb v ss to v pfd (min) v cc rise time 1 s t rec e1 or w at v ih or e2 at v il before power-up 1 ms t pfx int low to auto deselect 10 40 s t pfh v pfd (max) to int high 120 s symbol parameter (1)(2) 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.75 to 5.5 v or 4.5 to 5.5 v (except where noted). min typ max unit v pfd power-fail deselect voltage m48t08 4.5 4.6 4.75 v m48t18/t08y 4.2 4.3 4.5 v v so battery backup switchover voltage 3.0 v t dr expected data retention time 10 (3) 3. at 55c, v cc = 0 v; t dr = 8.5 years (typ) at 70c. requires use of m4t32-br12sh snaphat ? top when using the soh28 package. ye a r s
m48t08, m48t08y, m48t18 package mechanical data 23/31 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 13. pcdip28 ? 28-pin plastic dip, battery caphat ? , package outline note: drawing is not to scale. table 12. pcdip28 ? 28-pin plastic dip, battery caphat ? , package mech. data pcdip a2 a1 a l b1 b e1 d e n 1 c ea e3 symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 39.37 39.88 1.550 1.570 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 n28 28
package mechanical data m48t08, m48t08y, m48t18 24/31 figure 14. soh28 ? 28-lead plastic small outline, 4-socket battery snaphat ? , package outline note: drawing is not to scale. table 13. soh28 ? 28-lead plastic so, 4-socket battery snaphat ? , package mech. data soh-a e n d c l a1 1 h a cp be a2 eb symb mm inches typ min max typ min max a3.050.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 a0808 n28 28 cp 0.10 0.004
m48t08, m48t08y, m48t18 package mechanical data 25/31 figure 15. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package outline note: drawing is not to scale. table 14. sh ? 4-pin snaphat ? housing for 48 mah battery & crystal, package mech. data shtk-a a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a9.780.385 a1 6.73 7.24 0.265 0.285 a2 6.48 6.99 0.255 0.275 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 14.22 14.99 0.560 0.590 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090
package mechanical data m48t08, m48t08y, m48t18 26/31 figure 16. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package outline note: drawing is not to scale. table 15. sh ? 4-pin snaphat ? housing for 120 mah battery & crystal, package mech. data shtk-a a1 a d e ea eb a2 b l a3 symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090
m48t08, m48t08y, m48t18 part numbering 27/31 7 part numbering table 16. ordering information scheme caution: do not place the snaphat ? battery package ?m4txx-br12sh? in conductive foam as it will drain the lithium button-cell battery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m48t 18 ?100 pc 1 e device type m48t supply voltage and write protect voltage 08 (1) = v cc = 4.75 to 5.5 v; v pfd = 4.5 to 4.75 v 1. the m48t08/18 part is offered with the pcdip28 (e.g., caphat?) package only. 18/08y = v cc = 4.5 to 5.5 v; v pfd = 4.2 to 4.5 v speed ?100 = 100 ns ?150 = 150 ns ?10 = 100 ns (m48t08y) package pc (1) = pcdip28 mh (2) = soh28 2. the soic package (soh28) requires the snaphat ? battery/crystal package wh ich is ordered separately under the part number ?m4txx- br12sh? in plastic tube or ?m4txx-b r12shtr? in tape & reel form (see table 17 ). the m48t08y part is offered in the soh28 (snaphat) package only. temperature range 1 = 0 to 70c shipping method for soh28: blank = tubes (not for new design - use e) e = ecopack ? package, tubes f = ecopack ? package, tape & reel tr = tape & reel (not for new design - use f) for pcdip28: blank = ecopack ? package, tubes
part numbering m48t08, m48t08y, m48t18 28/31 table 17. snaphat ? battery table part number description package m4t28-br12sh lithium battery (48 mah) snaphat ? sh m4t32-br12sh lithium battery (120 mah) snaphat ? sh
m48t08, m48t08y, m48t18 environmental information 29/31 8 environmental information figure 17. recycling symbols this product contains a non-rechargeable lithi um (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. please refer to the following web site address for additional information regarding compliance statements and waste recycling. go to www.st.com/rtc , then select "lithium battery recycling" from "related topics".
revision history m48t08, m48t08y, m48t18 30/31 9 revision history table 18. document revision history date revision changes dec-1999 1 first issue 07-feb-2000 2 from preliminary data to datasheet; battery low flag paragraph changed; 100ns speed class identifier changed ( ta b l e 3 , 4 ) 11-jul-2000 2.1 t fb changed ( ta bl e 1 0 ); watchdog timer paragraph changed 16-jul-2001 3 reformatted; snaphat battery table added ( ta bl e 1 7 ); added temp./voltage info. to tables ( ta b l e 8 , 9 , 3 , 4 , 10 , 11 ). 01-aug-2001 3.1 reference to app. note corrected in ?calibrating the clock? section 21-dec-2001 3.2 changes to text in docum ent to reflect additi on of m48t08y option 06-mar-2002 3.3 fix ordering information table and add to footnote ( ta bl e 1 6 ) 20-may-2002 3.4 modify reflow time and temperature footnotes ( ta b l e 6 ) 29-aug-2002 3.5 t dr specification temperature updated ( ta b l e 1 1 ) 28-mar-2003 4 v2.2 template applied; updated test conditions ( ta bl e 1 0 ) 10-dec-2003 5 reformatted 30-mar-2004 6 reformatted; lead-free (pb-free) information package update ( ta bl e 6 , 16 ) 13-dec-2005 7 updated template, lead-free information, removed footnote ( ta bl e 9 , 16 ) 04-jul-2007 8 reformatted; added lead-free second level interconnect information to cover page and section 6: package mechanical data . 10-feb-2009 9 updated ta b l e 6 , text in section 6: package mechanical data ; added section 8: environmental information ; minor formatting changes.
m48t08, m48t08y, m48t18 31/31 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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